1. Field
The field of the present invention relates to particle beam lithography and, in particular, to logic design for cell projection particle beam lithography.
2. Description of Related Art
In today's semiconductor manufacturing process, optical lithography using photomasks is commonly used. However, mask cost, which is rapidly growing with shrinking feature size, is becoming a serious problem for semiconductor manufacturing. To solve this issue, various approaches that do not use a photomask, such as maskless lithography, have been proposed. One of the promising maskless lithography approaches is electron beam (EB) direct writing (EBDW). However, the problem with this approach has been its relatively low throughput, which has hindered its use for volume production. Thus, EBDW has been applied only for research and for interconnect layers of production application-specific integrated circuits (ASICs).
To reduce EB writing time, a cell projection (CP) technique has been proposed. Cell projection EB technology uses a stencil mask which contains cell patterns and which enables a cell pattern to be written or drawn by one shot, reducing overall writing time compared to the conventional variable shaped beam (VSB) method.
FIG. 1 shows a concept of cell projection EB writing. An electron beam source 100 projects an electron beam 102 that is formed into a rectangular shape 108 with a rectangular aperture 104 formed in a first aperture 106 and then is projected through a second aperture 110 formed in a stencil mask 112.
A conventional VSB machine usually uses relatively simple patterns as the apertures 110 of stencil mask 112 to form rectangular or triangular shapes with variable sizes and projects them onto a surface of a wafer or substrate 116. Design patterns 114 on the wafer 116 are formed by combinations of those simple rectangular or triangular shapes. On the other hand, in the case of cell projection, the stencil mask 112 may include more complex patterns as apertures 110 of the stencil mask 112. Each aperture pattern 110 can be any complex pattern of 10×10 square microns in size, as an example. Typical examples of such patterns contained on stencil masks are patterns of standard cell library entities such as logic gates or flip-flops.
FIG. 2 shows an example of the cell pattern layout 200 on a stencil mask 202 having a plurality of cell areas 204. The number of cell areas may be, for example, 100, depending on the cell area size. By choosing one of such cells, a cell pattern can be drawn on a wafer by one shot of EB exposure, compared to ten or more shots in the case of VSB, thus enabling writing time reduction.
However, the problem of CP is the limitation of the number of cells that can be contained in one stencil mask. Since the cell library of ASICs usually has 300 to 500 cells and the stencil mask should contain all the necessary orientations of each cell, all the cell patterns needed cannot be accommodated on the stencil mask. The limited number of cells on the stencil results in the case that only a part of the cells used in the integrated circuit or chip can be drawn with CP, which results in a limited throughput improvement.
Referring to FIG. 3, a conventional large scale integrated circuit (LSI) design flow 300 includes logic design and stencil design. In general, logic synthesis is used as a technique for optimally designing logic circuits, usually starting with a functional description 310, such as a register transfer level (RTL) description and various constraints 312 for the logic circuit design. The functional description 310 is first transformed into a logic circuit by logic transformation 322 and is then converted by technology mapping 324 to the final logic circuit 330, which consists of cell entities of a given cell library 304, which is pre-designed in step 302 for a given process technology, and which comprises a set of standard cells that have implementation details such as layout patterns and performance data.
In the course of the logic synthesis process 320, a set of parameters and constraints is used for optimization. Commonly used parameters and constraints include delay (timing information), power consumption, and area (physical size). After layout design 340, in the case of cell projection EB, a stencil mask 354 for CP is designed in step 350 and fabricated in step 352. In designing the stencil mask, frequently used cell patterns are included in the stencil as much as possible to reduce the EB writing time. Then, the layout design 340 and stencil design 350 are used for EB data preparation in step 360, and EB data 362 therefrom is used along with the stencil 354 to EB write and fabricate in step 370 the logic circuit 330 according to the layout design 340 on a wafer or substrate 380. This flow of LSI design and stencil design has been commonly applied for EB writing.
However, due to stencil capacity limitation, a substantial number of cells cannot be included in the stencil, forcing the patterns for these cells to be drawn by VSB shots. Thus, the writing time reduction by CP is limited. This is because no consideration on writing time is given during logic design process in the conventional design flow 300.
There currently exists a need to improve logic design for cell projection (CP) electron beam (EB) lithography.